FPGA RTL Design Engineer

UST

FPGA development and digital design.The candidate will be responsible for RTL design, implementation, verification, and FPGA bring-up for high-performance SoC/FPGA-based solutions.Perform FPGA synthesis, place & route, timing closure, and performance optimization.Develop and execute functional verif

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FPGA RTL Design Engineer

UST

Updated 1 day ago
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Bengaluru

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